Current - Issue
Year 2026 · Volume 6 · Issue 4
Original Article
FPGA Realization and Performance Evaluation of a 64-Bit RISC-V Processor
Ganavi D1
Dr. Manojkumar S B2
Sindhu D3
1 2 Department of E&C, BGS Institute of Technology, Adichunchanagiri University, B G Nagara, Karnataka, India. 3 Department of ISE, BGS Institute of Technology, Adichunchanagiri University, B G Nagara, Karnataka, India.
Published Online: July-August 2026
Pages: 139-145
Cite this article
↗ https://www.doi.org/10.59256/ijsreat.20260604015
References
1. Ma, K.-M., Le, D.-H., Pham, C.-K., & Hoang, T.-T. (2023). Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency
Lightweight Cryptographic Cores in FPGA. Future Internet, 15(5), 186.
2. Gugala, K. (2023). Enabling Collaborative Chip Design in the RISC-V VeeR Ecosystem. RISC-V Summit.
3. Perdomo, E., Kropotov, A., Cano, F., Zafar, S., Cervero, T., Martorell, X., & Salami, B. (2023). Makinote: An FPGA-Based HW/SW
Platform for Pre-Silicon Emulation of RISC-V Designs. arXiv preprint arXiv:2401.17984.
4. Gurung, S., & Shakya, S. (2023). Design and Implementation of RISC-V ISA (RV32IM) on FPGA. SSRG
5. International Journal of VLSI & Signal Processing, 10(2), 8 -14.
6. Kim, H.-J., & Kim, H.-J. (2023). A Design and Implementation of 32-bit RISC-V RV32IM Pipelined Processor Using FPGA. Journal of
the Korea Institute of Information and Communication Engineering, 27(1), 123 -130. Jo, S., Lee, J., & Kim, Y. (2022). A Design and
Implementation of 32 -bit Five-Stage RISC-V Processor Using FPGA. Journal of the Semiconductor & Display Technology, 21(4), 27
-32.
7. Kurth, A., Forsberg, B., & Benini, L. (2022). HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing. arXiv
preprint arXiv:2201.03861.
8. Sarkar, P., & Patel, V. K. S. (2022). 32-Bit RISC-V Pipelined Dual Core Processor: Design and Optimization. International Journal of
Creative Research Thoughts, 10(6), 670 -676.
9. Shariff, A. M. A., et al. (2022). Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review. International Journal
for Research in Applied Science & Engineering Technology, 10(6).
10. Sandeep, P. (2022). A Novel 32-Bit RISC-V Based Pipelined Processor Design Using Verilog. Bachelor's Thesis, Sathyabama Institute of
Science and Technology.
11. Bastian Koppelmann, et al., ”RISC-V Extension for Bit Manipulation Instructions”, 29th Proc. of International Symposium on Power and
Timing Modeling, Optimization and Simulation (PATMOS), 1 -3 July 2019, Rhodes, Greece.
12. Perdomo, E., Kropotov, A., Cano, F., Zafar, S., Cervero, T., Martorell, X., & Salami, B. (2024). Makinote: An FPGA-Based HW/SW
Platform for Pre-Silicon Emulation of RISC-V Designs. arXiv preprint arXiv:2401.17984
Lightweight Cryptographic Cores in FPGA. Future Internet, 15(5), 186.
2. Gugala, K. (2023). Enabling Collaborative Chip Design in the RISC-V VeeR Ecosystem. RISC-V Summit.
3. Perdomo, E., Kropotov, A., Cano, F., Zafar, S., Cervero, T., Martorell, X., & Salami, B. (2023). Makinote: An FPGA-Based HW/SW
Platform for Pre-Silicon Emulation of RISC-V Designs. arXiv preprint arXiv:2401.17984.
4. Gurung, S., & Shakya, S. (2023). Design and Implementation of RISC-V ISA (RV32IM) on FPGA. SSRG
5. International Journal of VLSI & Signal Processing, 10(2), 8 -14.
6. Kim, H.-J., & Kim, H.-J. (2023). A Design and Implementation of 32-bit RISC-V RV32IM Pipelined Processor Using FPGA. Journal of
the Korea Institute of Information and Communication Engineering, 27(1), 123 -130. Jo, S., Lee, J., & Kim, Y. (2022). A Design and
Implementation of 32 -bit Five-Stage RISC-V Processor Using FPGA. Journal of the Semiconductor & Display Technology, 21(4), 27
-32.
7. Kurth, A., Forsberg, B., & Benini, L. (2022). HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing. arXiv
preprint arXiv:2201.03861.
8. Sarkar, P., & Patel, V. K. S. (2022). 32-Bit RISC-V Pipelined Dual Core Processor: Design and Optimization. International Journal of
Creative Research Thoughts, 10(6), 670 -676.
9. Shariff, A. M. A., et al. (2022). Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review. International Journal
for Research in Applied Science & Engineering Technology, 10(6).
10. Sandeep, P. (2022). A Novel 32-Bit RISC-V Based Pipelined Processor Design Using Verilog. Bachelor's Thesis, Sathyabama Institute of
Science and Technology.
11. Bastian Koppelmann, et al., ”RISC-V Extension for Bit Manipulation Instructions”, 29th Proc. of International Symposium on Power and
Timing Modeling, Optimization and Simulation (PATMOS), 1 -3 July 2019, Rhodes, Greece.
12. Perdomo, E., Kropotov, A., Cano, F., Zafar, S., Cervero, T., Martorell, X., & Salami, B. (2024). Makinote: An FPGA-Based HW/SW
Platform for Pre-Silicon Emulation of RISC-V Designs. arXiv preprint arXiv:2401.17984
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