Current - Issue

1. Meher PK, Chandrasekaran S, Amira A. FPGA realization of FIR filters by efficient and flexible distributed arithmetic. IEEE
Transactions on Signal Processing. 2008;56(7):3009–3017.
2. White S. Applications of distributed arithmetic to digital signal processing: A tutorial review. IEEE ASSP Magazine. 1989;6(3):4–19.
3. Peled A, Liu B. A new hardware realization of digital filters. IEEE Transactions on Acoustics, Speech, and Signal Processing.
1974;22(6):456–462.
4. Meher PK. New approach to LUT implementation of FIR digital filters using distributed arithmetic. IEEE Transactions on Circuits and
Systems II: Express Briefs. 2007;54(3):262–266.
5. Sutter G, Sutter C, Laforest F. Efficient FPGA implementation of FIR filters using distributed arithmetic. IEEE International Conference
on Field Programmable Logic and Applications (FPL). 2009:1–6.
6. Kumm M, Zipf P, Lehner W. Low-power FPGA implementation of FIR filters using distributed arithmetic. IEEE International Conference
on Field-Programmable Technology. 2007:1–8.
7. Chen J, Wang J, Chen C. Low-power and high-speed FIR filter implementation based on distributed arithmetic. IEEE Transactions on Very
Large Scale Integration (VLSI) Systems. 2012;20(5):970–974.
8. Liu W, Nannarelli A. Power-efficient FIR filter implementation using approximate computing. IEEE Transactions on Circuits and
Systems II: Express Briefs. 2016;63(12):1137–1141.
9. Venkataramani S, Chakradhar S, Roy K, Raghunathan A. Approximate computing and the quest for computing efficiency. Design
Automation Conference (DAC). 2015:1–6.
10. Mrazek V, Sarwar SS, Sekanina L, Vasicek Z, Roy K. Design of power-efficient approximate multipliers for approximate
computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017;25(4):1346–1358.
11. Gupta V, Mohapatra D, Park S, Raghunathan A, Roy K. IMPACT: IMPrecise adders for low-power approximate computing. IEEE/ACM
International Symposium on Low Power Electronics and Design (ISLPED). 2011:409–414.
12. Jiang H, Liu C, Lombardi F, Han J. Low-power approximate unsigned multipliers with configurable accuracy. IEEE Transactions on
Computers. 2018;67(1):94–107.
13. Xilinx Inc. Vivado Design Suite User Guide: Synthesis. Xilinx Technical Documentation. 2020. Mittal S. A survey of techniques for
approximate computing. ACM Computing Surveys. 2016;48(4):1–33.
14. Hegde RS, Shanbhag NR. Soft digital signal processing using error-tolerant techniques. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems. 2009;17(10):1425–1437.
15. Bruguera JD. Arithmetic Logic in VLSI. Cambridge University Press; 2001.
16. Proakis JG, Manolakis DG. Digital Signal Processing: Principles, Algorithms, and Applications. 4th ed. Pearson Education;
2007.
17. Oppenheim AV, Schafer RW. Discrete-Time Signal Processing. 3rd ed. Pearson Education; 2010.
18. Smith SW. The Scientist and Engineer's Guide to Digital Signal Processing. California Technical Publishing; 1997.
19. Xilinx Inc. 7 Series FPGAs Data Sheet: Overview. Xilinx Technical Documentation; 2021.