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Original Article
FPGA Realization and Performance Evaluation of a 64-Bit RISC-V Processor
Ganavi D1
Dr. Manojkumar S B2
Sindhu D3
1 2 Department of E&C, BGS Institute of Technology, Adichunchanagiri University, B G Nagara, Karnataka, India. 3 Department of ISE, BGS Institute of Technology, Adichunchanagiri University, B G Nagara, Karnataka, India.
Published Online: July-August 2026
Pages: 139-145
Cite this article
↗ https://www.doi.org/10.59256/ijsreat.20260604015
Abstract
RISC-V is an open-standard instruction set architecture (ISA) that has gained widespread adoption due to its modular design, scalability, and flexibility across diverse computing platforms. The 64-bit RISC-V architecture (RV64I) extends the capabilities of the base ISA by supporting larger address spaces, higher computational precision, and improved performance for modern computing workloads. It is compatible with widely used software ecosystems such as GNU, LLVM, QEMU, Spike, and other open-source development tools, making it suitable for both research and commercial applications.
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