ARCHIVES

1. Z. Ding, D. Zhang, and D. Wang, "A Hardware Architecture for Shared Residuals and Simplified Symmetric-PWL-Based GELU," in
Proc. 2024 IEEE 17th Int. Conf. on ASIC (ASICON), 2024.
2. T. Mohaidat, M. R. Kader Khan, and K. Khalil, "Curvature-Based Piecewise Linear Approximation Method of GELU Activation
Function in Neural Networks," in Proc. 2024 2nd Int. Conf., IEEE, 2024.
3. Shobana T. S., Rashmi K. B., S. R. Akamanchi, S. Pandey, P. Bhat, and S. Naik Charan, "Brain Tumour Analysis of MRI Images with
a CNN Architecture Using Hybrid SiLU+GELU Activation Function," in Proc. 2026 2nd Int. Conf., IEEE, 2026.
4. B. Erdem Altuntas, O. Aksu, M. Yigitcan Celik, and M. H. Durak, "Deep Learning Based Automatic Modulation Recognition Using
GELU Activation Function," in Proc. 2024 4th Int. Conf., IEEE, 2024.
5. M. Labied, A. Belangour, and M. Banane, "P-GELU: A Novel Activation Function to Optimize Whisper for Darija Speech Translation,"
IEEE Access, vol. 13, 2025.
6. "High-Precision and Efficiency Hardware Implementation for GELU Activation Function," Electronics (MDPI), vol. 14, no. 9, art. 1825,
2025.
7. "A CORDIC-Based Configurable Activation Function for Neural Network Acceleration (DA-VINCI)," arXiv:2503.14354, 2025.
8. "CORDIC Is All You Need: A Reconfigurable Systolic Engine for MAC and Activation Functions," arXiv:2503.11685, 2025.
9. "EBACA: Efficient Bfloat16-Based Activation Function Implementation Using Enhanced CORDIC Architecture," in Proc. IEEE Int.
Conf., 2024.
10. "Efficient FPGA Realization of Neural Network Activation Functions Using Adaptive Piecewise Polynomial Approximations with
Chebyshev Nodes," Results in Engineering (Elsevier), 2025.
11. "An Area-Efficient and Low-Error FPGA-Based Sigmoid Function Approximation," Applied Sciences (MDPI), vol. 15, no. 21, art.
11551, 2025.
12. "Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function," Sensors (MDPI), vol. 24, no. 6,
art. 1829, 2024.
13. "A Reconfigurable Multi-Precision Quantization-Aware Nonlinear Activation Function Hardware Module for Deep Neural Networks,"
Elsevier, 2024.
14. "Hardware-Friendly and Efficient Vision Transformer for Deployment on Low-Power Embedded Devices," J. Low Power Electronics
and Applications (MDPI), vol. 16, no. 1, 2025.
15. "1D-CNN-Transformer for Radar Emitter Identification and Implemented on FPGA," Remote Sensing (MDPI), vol. 16, no. 16, art. 2962,
2024.
16. "High-Throughput Instruction–Data-Level Parallelism-Based Arithmetic Hardware Accelerator Using CORDIC," Int. J. Parallel
Programming (Springer), 2025.
17. "2QGRU: Power-of-Two Quantization for Efficient FPGA-Based Gated Recurrent Unit Architectures," Electronics (MDPI), vol. 15, no.
4, art. 722, 2026.
18. "DAPA: Distribution-Aware Piecewise Activation Functions for FPGA," arXiv:2603.19338, 2026.