Design of Power and Area Efficient Approximate Multiplier

Mutyala Athiradh; M L V V S M Ramakrishina; Dr. V. Balamurugan

doi:10.59256/ijsreat.20260602020

Original Article

Design of Power and Area Efficient Approximate Multiplier

Paper ID 293
Volume 6, Issue 2
Pages 138-143
Published Online: March-April 2026
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Authors

Mutyala Athiradh¹
M L V V S M Ramakrishina²
Dr. V. Balamurugan³

¹ ² UG Scholar, Department of Electronics and Communication Engineering, Sathyabhma Institute of Science and Technology, Chennai, Tamil Nadu, India. ³ Professor, Department of Electronics and Communication Engineering, Sathyabhma Institute of Science and Technology, Chennai, Tamil Nadu, India.

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Article Information

DOI: https://www.doi.org/10.59256/ijsreat.20260602020
Published In: Volume 6, Issue 2 (2026)
Published Online: March-April 2026
Pages: 138-143
Article Type: Original Article
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Citations

Mutyala Athiradh1, M L V V S M Ramakrishina2, Dr. V. Balamurugan3 “Design of Power and Area Efficient Approximate Multiplier ”, International Journal of Scientific Research in Engineering & Technology, Volume 06, Issue 02, March-April 2026, PP: 138-143.

Design of Power and Area Efficient Approximate Multiplier

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