Design of Power and Area Efficient Approximate Multiplier

DOI

https://www.doi.org/10.59256/ijsreat.20260602020

Published In

Volume 6, Issue 2 (2026)

Published Online

March-April 2026

Pages

138-143

Article Type

Original Article

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Approximate Computing has become a popular technique for designing low-power, area-efficient digital circuits for use in error-tolerant applications, such as image and signal processing and machine learning. Multipliers are one of the main building blocks of arithmetic components and contribute greatly to both overall power consumption and silicon area. In this work, we describe the design and implementation of an efficient (in terms of area and power) approximate multiplier by inserting an approximate of the partial product generation stage. More specifically, some of the AND gates of the proposed architecture are replaced with OR gates, with most significant reduction occurring on the least significant bits positions, thus reducing the number of transistors, switching activity and logic complexity but maintaining the accuracy of the most significant bits. The proposed approximate multiplier was implemented and validated at the transistor level. Functionality verification was conducted through simulation. A comparison of the performance of the approximate multiplier to the performance of a traditional exact multiplier shows that using the technique described results in a large reduction in power consumption and hardware complexity while sustaining an acceptable level of computational accuracy. Overall, the results of this work show that there is a large trade-off between accuracy and efficiency in using approximate multipliers for error-tolerant and low-power VLSI applications.